The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A device, such as a computer, a mobile phone, a tablet, etc., can include a processor, cache memory and nonvolatile memory. The processor may include the cache memory or alternatively the cache memory may be arranged in close proximity to the processor. The cache memory can include one or more of a level zero (L0) cache, a level one (L1) cache, a level two (L2) cache, or a level three (L3) cache. Close arrangement of the cache memory to the processor provides quick access to data stored in the cache memory. Data stored in the cache memory can also be stored in the other storage devices. The nonvolatile memory can include random access memory (RAM), solid-state memory, a storage drive, a hard disk drive, etc.
The cache memory can be used to temporarily store a copy or a version of data stored in the nonvolatile memory. Due to the close proximity of the cache to the processor, the processor is able to more quickly access the data stored in the cache as opposed to the corresponding data stored in the nonvolatile memory.
FIG. 1 shows a portion 10 of a cache including multiple arrays 12 of storage elements 14 storing respective cache lines, and data access modules 16. The storage elements 14 include “cache lines”. Each cache line can refer to a contiguous range of memory locations. Each of the cache lines is included in a corresponding one of the arrays 12, has a corresponding index, and can store multiple segments of data. Each of the segments can include a predetermined number of bits, bytes and/or words of data. In the example shown, each cache line includes 4 words [3:0]. Each word is one segment of the corresponding cache line.
The cache lines are grouped into sets of storage elements (hereinafter referred to as “sets”) and ways of storage elements (hereinafter referred to as “ways”). The sets are identified by respective indices. Data stored in a cache line and corresponding to a particular range of cache line addresses can only be stored in a particular set, but may be stored in any one of the ways. Each of the sets refers to possible locations in a cache where certain data bits can be stored. Each of the ways refers to storage elements of a particular array and includes a storage element in each of the sets. For the example shown, the cache is a 4-way/8-set cache.
The data access modules 16 of each array accesses data stored in the corresponding way. Each of the data access modules 16 includes sense amplifiers and/or write drivers. The sense amplifiers and write drivers of an array access corresponding storage elements of that array. The storage elements of an array are not accessed in parallel. The storage elements of multiple arrays can be accessed in parallel.
Sizes of the cache lines can be optimized for access efficiency purposes. As an example, addresses and/or states of each cache line can be tracked. To store the tracked addresses and/or states of the cache lines, in addition to the corresponding data, sizes of the cache lines can be increased. Each cache line may store one or more addresses and states of that cache line. The addresses, states and data of a cache line can then be accessed from the cache line, which increases efficiency. Also, increasing sizes of the cache lines can result in more efficient transfers of data to and from a cache when spatial locality of accesses is such that cache line addresses are within a predetermined range of each other. However, the larger the cache lines of a cache, the fewer locations available to store the data and as a result the more limited is the flexibility of where the data can be stored.